Mixed-Signal/RF Integrated Circuits Seminar Series A 25MS/s 14b Sigma-Delta Modulator for VDSL

Up to the present, several attempts have been made to increase the conversion rate by minimizing the oversampling ratio, but another important aspect has been somehow overlooked, i.e., the maximization of the sampling frequency. In this design both aspects are instead considered. Since the specifications of the analog building blocks are determined by the selected architecture, the choice of an architecture that puts low speed specifications on the analog building blocks despite high sampling rates constitutes a central point in this design. Furthermore, sufficient dynamic range at low oversampling ratio is provided as well.The modulator is implemented in a 1 poly, 6 metals 0.18um CMOS technology with MIM capacitor option. The measured peak SNR and SNDR are 82dB and 72dB respectively, the dynamic range is 84dB. Conversion rate and sampling frequency are 25MS/s and 200MHz, respectively. The core chip area is about 1mm, the total power consumption is 200mW, including the consumption of a fast reference buffer.